1. Field of the Invention
This invention concerns a process for the control of a first input-first output (FIFO) type circuit, this FIFO circuit being used to manage a large number of data. This invention also concerns a device for the embodiment of this process.
The process and the control device for the FIFO circuit conform with this invention have been developed to manage a circuit in order to store a complete line of a video signal forming part of an HD MAC signal. However it will be obvious to the expert in the field that this FIFO circuit could be used for other applications.
2. Description of the Prior Art
Thus for an HD MAC picture, a video line generally contains 1296 9-bit words that will be sub-sampled so as to respect Shanon's theorem. Consequently in order to process an HD MAC video line, it must be possible to store at least 2592 9-bit words in a circuit that must be written at 40.5 MHz. Moreover, in order to perform a number of procedures or corrections on the video signal thus stored, the signal has to be sent to an external microcontroller. This is generally done using a bus with a data exchange rate varying between 100 kbits per second and 400 Kbits per second for the fastest buses. It is therefore read at a slower speed than it is written. In this case, a number of circuits may be used to store the video line. In particular, a RAM type memory circuit can be used with demultiplexed inputs and multiplexed outputs in order to write at 40.5 MHz.
However, the management of multiplexed inputs and demultiplexed outputs is complex and requires the use of several different clock signals. Moreover, this part requires a large number of transistors for its manufacture.
Consequently, the idea of using a first input-first output type circuit made by shift registers was conceived in order to store an HD MAC type video line. However, the use of shift registers as a storage circuit requires the use of two stages for information to be stored in order to avoid losing this information. Therefore the capacity of the shift register has to be doubled.